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1/32 preliminary data october 2003 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. m69ar024b 16 mbit (1m x16) 1.8v supply, asynchronous psram features summary n supply voltage: 1.7 to 1.95v n access time: 70ns, 80ns n low standby current: 100 a n deep power down current: 10a n compatible with standard lpsram n tri-state common i/o figure 1. packages fbga tfbga48 (zb) 6x8mm
m69ar024b 2/32 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 deep power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 table 5. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 7. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. address and output enable controlled, read mode ac waveforms . . . . . . . . . . . . . . . 14 figure 9. lb/ub controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. write enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. write enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. write enable and ub/lb controlled, write ac waveforms 1 . . . . . . . . . . . . . . . . . . . . 19 figure 13. write enable and ub/lb controlled, write ac waveforms 2 . . . . . . . . . . . . . . . . . . . . 20 figure 14. write enable and ub/lb controlled, write ac waveforms 3 . . . . . . . . . . . . . . . . . . . . 21 figure 15. write enable and ub/lb controlled, write ac waveforms 4 . . . . . . . . . . . . . . . . . . . . 22 figure 16. chip enable controlled, read and write mode ac waveforms . . . . . . . . . . . . . . . . . . 23 figure 17. chip enable, write enable, output enable controlled, read and write mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 18. output enable and write enable controlled, read and write mode ac waveforms . . 25 figure 19. output enable, write enable and ub/lb controlled, read and write mode ac waveforms 26 table 9. standby mode ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/32 m69ar024b figure 20. power down mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 21. power-up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 22. standby mode entry ac waveforms, after read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 tfbga48 6x8mm - 6x8 active ball array, 0.75 mm pitch, package outline, bottom view . . . . . . . 29 tfbga48 6x8mm - 6x8 active ball array, 0.75 mm pitch, package mechanical data . . . . . . . . . . 29 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
m69ar024b 4/32 summary description the m69ar024b is a 16 mbit (16,777,216 bit) cmos memory, organized as 1,024,576 words by 16 bits, and is supplied by a single 1.7v to 1.95v supply voltage range. m69ar024b is a member of stmicroelectronics 1t/1c (one transistor per cell) memory family. these devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area. however, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard asynchronous sram interface. the internal control logic of the m69ar024b han- dles the periodic refresh cycle, automatically, and without user involvement. write cycles can be performed on a single byte by using upper byte enable (ub ) and lower byte en- able (lb ). the device can be put into standby mode using chip enable (e1 ) or in deep power down mode by using chip enable (e2). power-down mode achieves a very low current consumption by halting all the internal activities. since the refresh circuitry is halted, the duration of the power-down should be less than the maximum period for refresh, if the user has not finished with the data contents of the memory. figure 2. logic diagram table 1. signal names ai07260 20 a0-a19 w dq0-dq15 v cc m69ar024b g 16 e1 ub lb v ss e2 a0-a19 address inputs dq0-dq15 data input/output e1 , e2 chip enable g output enable w write enable ub upper byte enable input lb lower byte enable input v cc supply voltage v ss ground nc not connected (no internal connection)
5/32 m69ar024b figure 3. tfbga connections (top view through package) ai05861b a 6 5 4 3 2 1 e b f a1 a0 g lb a17 dq7 w a12 nc a11 a8 a18 dq0 a3 a6 a5 a4 e1 a10 a9 a13 a7 a2 e2 c dq4 d dq5 a14 a15 g h dq11 a19 ub dq10 dq12 dq13 v ss dq15 dq8 dq9 dq14 dq3 dq2 dq1 v cc v cc nc v ss dq6 a16
m69ar024b 6/32 signal descriptions see figure 2, logic diagram, and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a19). the address inputs select the cells in the memory array to access dur- ing read and write operations. data inputs/outputs (dq8-dq15). the upper byte data inputs/outputs carry the data to or from the upper part of the selected address during a write or read operation, when upper byte enable (ub ) is driven low. data inputs/outputs (dq0-dq7). the lower byte data inputs/outputs carry the data to or from the lower part of the selected address during a write or read operation, when lower byte enable (lb ) is driven low. chip enable (e1 ). when asserted (low), the chip enable, e1 , activates the memory state ma- chine, address buffers and decoders, allowing read and write operations to be performed. when de-asserted (high), all other pins are ignored, and the device is put, automatically, in low-power standby mode. chip enable (e2). the chip enable, e2, puts the device in deep power-down mode when it is driven low. this is the lowest power mode. output enable (g ). the output enable, g , pro- vides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. write enable (w ). the write enable, w , controls the bus write operation of the memorys com- mand interface. upper byte enable (ub ). the upper byte en- able, ub , gates the data on the upper byte data inputs/outputs (dq8-dq15) to or from the upper part of the selected address during a write or read operation. lower byte enable (lb ). the lower byte en- able, lb , gates the data on the lower byte data inputs/outputs (dq0-dq7) to or from the lower part of the selected address during a write or read operation. v cc supply voltage. the v cc supply voltage supplies the power for all operations (read or write) and for driving the refresh logic, even when the device is not being accessed. vss ground. the v ss ground is the reference for all voltage measurements.
7/32 m69ar024b figure 4. block diagram ai07261b dynamic memory array row decoder column decoder control logic e1 refresh controller arbitration logic internal clock generator input/output buffer address ub e2 g w lb power controller v cc v ss address dq0-dq7 dq8-dq15
m69ar024b 8/32 table 2. operating modes note: 1. x = v ih or v il . 2. should not be kept in this logic condition longer than 1s. please contact your local st sales office for the relaxation of 1s limitation. 3. power-down mode can be entered from the standby state, and all dq pins are in high-z state. i pd current and data retention de- pend on the selection of power down program. see "power down program" for the detail. 4. can be either vil or vih but must be valid before read or write. operation e2 e1 w g lb ub a0-a19 dq0-dq7 dq8-dq15 i cc data re- tention standby (deselect) v ih v ih x (1) x (1) x (1) x (1) x (1) hi-z hi-z i sb ye s output disabled v ih v il v ih v ih x (1) x (1) note (4) hi-z hi-z i cc ye s output disabled (no read) (2) v ih v il v ih v il v ih v ih valid hi-z hi-z i cc ye s upper byte read (2) v ih v il v ih v il v ih v il valid hi-z output valid i cc ye s lower byte read (2) v ih v il v ih v il v il v ih valid output valid hi-z i cc ye s word read (2) v ih v il v ih v il v il v il valid output valid output valid i cc ye s no write (2) v ih v il v il v ih v ih v ih valid invalid invalid i cc ye s upper byte write (2) v ih v il v il v ih v ih v il valid invalid input valid i cc ye s lower byte write (2) v ih v il v il v ih v il v ih valid input valid invalid i cc ye s word write (2) v ih v il v il v ih v il v il valid input valid input valid i cc ye s power-down (3) v il x (1) x (1) x (1) x (1) x (1) x (1) hi-z hi-z i pd yes/no
9/32 m69ar024b operation operational modes are determined by device con- trol inputs w , e1 , e2, lb and ub as summarized in the operating modes table (see table 2). power on sequence because the internal control logic of the m69ar024b needs to be initialized, the following power-on procedure must be followed before the memory is used: C apply power and wait for v cc to stabilize C wait 300s while driving both chip enable signals (e1 and e2) high read mode the device is in read mode when: C write enable (w ) is high and C output enable (g ) low and C upper byte enable (ub ) or lower byte en- able (lb ) is low, or both C the two chip enable signals are asserted (e1 is low, and e2 is high). the time taken to enter read mode (t elqv , t glqv or t blqv ) depends on which of the above signals was the last to reach the appropriate level. data out (dq15-dq0) may be indeterminate during t elqx , t glqx and t blqx , but data will always be valid during t avqv . write mode the device is in write mode when C write enable (w ) is low and C chip enable (e1 ) is low and C upper byte enable (ub ) or lower byte en- able (lb ) is low, or both C the two chip enable signals are asserted (e1 is low, and e2 is high). the write cycle begins just after the event (the fall- ing edge) that causes the last of these conditions to become true (t avwl or t avel or t avbl ). the write cycle is terminated by the earlier of a ris- ing edge on write enable (w ) or chip enable (e1 ). if the device is in write mode (chip enable (e1 ) is low, output enable (g ) is low, upper byte en- able (ub ) or lower byte enable (lb ) is low), then write enable (w ) will return the outputs to high im- pedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of op- eration. data input must be valid for t dvwh before the rising edge of write enable (w ), or for t dveh before the rising edge of chip enable (e1 ), which- ever occurs first, and remain valid for t whdx , t ehdx standby mode the device is in standby mode when: C chip enable (e1 ) is high and C chip enable (e2) is high the input/output buffers and the decoding/control logic are switched off, but the dynamic array con- tinues to be refreshed. in this mode, the memory current consumption, i sb , is reduced, and the data remains valid. deep power-down mode the device is in deep power-down mode when: C chip enable (e2) is low
m69ar024b 10/32 maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. table 3. absolute maximum ratings note: 1. the minimum dc voltage on input or i/o pins is C0.3v. during voltage transitions, inputs may undershoot v ss by 1.0v for periods of up to 5ns. 2. the maximum dc voltage on input and i/o pins is v cc +0.2v. during voltage transitions, inputs may overshoot v cc by 1.0v for periods of up to 5ns. symbol parameter min max unit i o output current C50 50 ma t a ambient operating temperature C25 85 c t stg storage temperature C55 125 c v cc core supply voltage C0.2 3.3 v v io (1,2) input or output voltage C0.2 3.3 v
11/32 m69ar024b dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 4. operating and ac measurement conditions note: 1. all voltages are referenced to v ss . figure 5. ac measurement i/o waveform figure 6. ac measurement load circuit parameter m69ar024b unit min max v cc supply voltage 1 1.7 1.95 v ambient operating temperature C25 85 c load capacitance (c l ) 50 pf output circuit protection resistance (r 1 ) 50 w input pulse voltages 0 to v cc v input and output timing ref. voltages v cc /2 v output transition timing ref. voltages v rl = 0.3v cc ; v rh = 0.7v cc v ai04831 v cc i/o timing reference voltage 0v v cc /2 v cc output timing reference voltage 0v 0.7v cc 0.3v cc ai07222b v cc /2 out c l includes jig capacitance device under test c l r 1
m69ar024b 12/32 table 5. capacitance note: 1. sampled only, not 100% tested. 2. outputs deselected. table 6. dc characteristics note: 1. the maximum dc voltage on input and i/o pins is v cc +0.2v. during voltage transitions, inputs may overshoot v cc by 1.0v for periods of up to 5ns. 2. the minimum dc voltage on input or i/o pins is C0.3v. during voltage transitions, inputs may undershoot v ss by 1.0v for periods of up to 5ns. symbol parameter (1,2) test condition min max unit c in input capacitance on all pins (except dq) v in = 0v 5pf c out (2) output capacitance v out = 0v 8pf symbol parameter test condition min max unit i cc1 v cc active current v cc = 1.95v, v in = v ih or v il , e1 = v il and e2 = v ih , i out = 0ma t avav read / t avav write = minimum 15 ma i cc2 t avav read / t avav write = maximum 3ma i li input leakage current 0v v in v cc C1 1 a i lo output leakage current 0v v out v cc C1 1 a i pd deep power down current v cc = 1.95v, e1 3 v cc C0.2v or e1 v il , v in 3 v cc C0.2v or v in 0.2v 10 a i sb standby supply current cmos v cc = 1.95v, e1 = e2 3 v cc C0.3v, i out = 0ma 100 a v ih (1) input high voltage 0.8v cc v cc + 0.2 v v il (2) input low voltage C0.2 0.4 v v oh output high voltage i oh = C0.1ma v cc C 0.2 v v ol output low voltage i ol = 0.1ma 0.2 v
13/32 m69ar024b table 7. read mode ac characteristics note: 1. maximum value is applicable if e 1 is kept at low without change of address input of a3 to a19. if needed by system operation, please contact local st sales office for the relaxation of 1s limitation. 2. address should not be changed within tavax(min). 3. the output load 50pf with 50 w termination to v cc *0.5 v. 4. the output load c l = 5pf without any other load. 5. applicable to a3 to a19 when e 1 is kept at low. 6. applicable only to a0, a1 and a2 when e 1 is kept at low for the page address access. 7. in case page read cycle is continued with keeping e 1 stays low, e 1 must be brought to high within 4s. in other words, page read cycle must be closed within 4s. 8. applicable when at least two of address inputs among applicable are switched from previous state. 9. tavax(min) must be satisfied. symbol alt. parameter m69ar024b unit -70 -80 min max min max t avax (1,2) t rc address valid time 80 1000 80 1000 ns t avel t asc address valid to chip enable low C5 C5 ns t avgl t aso address valid to output enable low 10 10 ns t avqv (3,5) t aa address valid to output valid 70 80 ns t axav (5,8) t ax address invalid time 10 10 ns t axqx (3) t oh data hold from address change 10 10 ns t bhqx (3) t oh upper/lower byte enable high to output transition 10 10 ns t bhqz (4) t bhz upper/lower byte enable high to output hi-z 20 20 ns t blqv (3) t ba upper/lower byte enable low to output valid 70 80 ns t blqx (4) t blz upper/lower byte enable low to output transition 5 5 ns t ehax (9) t chah chip enable high to address invalid C5 C5 ns t ehel t cp chip enable high to chip enable low 15 15 ns t ehqx (3) t oh chip enable high to output transition 10 10 ns t ehqz (4) t chz chip enable high to output hi-z 20 20 ns t elax (1,2) t rc read cycle time 80 1000 80 1000 ns t eleh (1,2) t rc read cycle time 80 1000 80 1000 ns t elqv (3) t ce chip enable low to output valid 70 80 ns t elqx (4) t clz chip enable low to output transition 10 10 ns t ghax t ohah output enable high to address invalid C5 C5 ns t ghqx (3) t oh output data hold time 10 10 ns t ghqz (4) t ohz output enable high to output hi-z 20 20 ns t glqv (3) t oe output enable low to output valid 45 45 ns t glqx (4) t olz output enable low to output transition 5 5 ns
m69ar024b 14/32 figure 7. address controlled, read mode ac waveforms note: e2 = high, w = high. figure 8. address and output enable controlled, read mode ac waveforms note: w = high, e2 = high. ai04819c t e lqv valid data output address e 1 dq (output) g t e h qx t eleh t e l qx t e ha x t ehel address valid t a vel t a vel t g h q x t ehqx t bh q x lb / ub t glqv t b lqv t bl qx t g l qx ai05863c t a vqv valid data output address e 1 dq (output) lb / ub t g h q z t glqv t avax t g l qx address valid valid data output address valid t avax t axqx t g h qx g t ax av t ax av low t a vqv t ax av
15/32 m69ar024b figure 9. lb /ub controlled, read mode ac waveforms note: e1 = low, e2 = high, g = low, w = high. ai07497b t a vqv valid data output address dq0-7 (output) ub t bh q z t b lqv t avax t bl qx address valid valid data output t bh q z t b h qx lb t ax av t b lqv t ax av dq8-15 (output) t bl qx t b lqv t bl qx t b h qx t bh q z t b h qx valid data output
m69ar024b 16/32 table 8. write mode ac characteristics note: 1. maximum value is applicable if e1 is kept at low without any address change. if needed by system operation, please contact your local st representative for relaxation of the 1000ns limitation. 2. minimum value must be equal to or greater than the sum of write pulse (teleh, twlwh or tblbh) and write recovery time (twrc, twr or tbr). 3. write pulse is defined from the falling edge of e1 , w , or lb /ub , whichever occurs last. 4. write recovery is defined from write pulse is defined from the rising edge of e1 , w , or lb /ub , whichever occurs first. 5. applicable to any address change when e1 stays low. 6. if g is low after minimum tghel, the read cycle is initiated. in other words, g must be brought high within 5ns after e1 is brought low. once the read cycle is initiated, new write pulse should be input after minimum read cycle time is met. 7. if g is low after new address input, the read cycle is initiated. in other words, g must be brought high at the same time or before new address valid. once the read cycle is initiated, new write pulse should be input after minimum read cycle time is met. symbol alt. parameter m69ar024b unit -70, -80 min max t avax (1,2) t wc write cycle time 80 1000 ns t avb l (2) t as address valid to lb , ub low 0 ns t ave l (2) t as address valid to chip enable low 0 ns t avw l (2) t as address valid to write enable low 0 ns t axav (5) t axw address invalid time for write 10 ns t bhax (4) t br lb , ub high to address transition 15 1000 ns t bhdx t dh lb , ub high to input transition 0 ns t blbh (3) t bw lb , ub low to lb , ub high 75 ns t blbh2 t bwo lb , ub low to lb , ub high, pulse overlap 20 ns t blwh (3) t bw lb , ub low to write enable high 75 ns t dvbh t ds input valid to lb , ub high 30 ns t dveh t ds input valid to chip enable high 30 ns t dvwh t ds input valid to write enable high 30 ns t ehax (4) t wrc chip enable high to address transition 15 ns t ehdx t dh chip enable high to input transition 0 ns t ehel t cp chip enable high to chip enable low 15 ns t elax (1,2) t wc write cycle time 80 1000 ns t eleh (3) t cw chip enable low to chip enable high 75 ns t ghav (7) t oes output enable high to address valid 0 ns t ghel (6) t ohcl output enable high to chip enable low C5 ns t whax (4) t wr write enable high to address transition 15 1000 ns t whdx t dh write enable high to input transition 0 ns t wlbh (3) t wp write enable low to lb , ub high 65 ns t wlwh (3) t wp write enable low to write enable high 65 1000 ns
17/32 m69ar024b figure 10. write enable controlled, write ac waveforms note: e2 = high. ai05865c t a vel valid data input address e 1 dq (input) w t ehdx,whdx,bhdx t dveh,dvwh,dvbh t elax t ehax t w lwh t eleh lb , ub t a vbl t b lbh address valid t a vel t a vwl t b hax g t g h e l t a vwl t a vbl t w hax
m69ar024b 18/32 figure 11. write enable controlled, write ac waveforms note: e2 = high. ai05866c t a vwl address w e 1 t a vax t w hax t w lwh lb , ub address valid t a vwl t w hax t w lwh valid data input dq (input) t w h dx t d vwh g t ghav t g h q z t avax t ax av valid data input t w h dx t d vwh low address valid
19/32 m69ar024b figure 12. write enable and ub /lb controlled, write ac waveforms 1 note: e2 = high. ai07492b t a vwl address w e 1 t avax t bhax t w lbh lb address valid t a vwl t bhax t w lbh valid data input dq0-7 (input) t bhdx t d vbh ub t avax t ax av valid data input t b h dx t d vbh low address valid dq8-15 (input)
m69ar024b 20/32 figure 13. write enable and ub /lb controlled, write ac waveforms 2 note: e2 = high. ai07491b t a vbl address w e 1 t avax t w hax t b l w h lb address valid t a vbl t ax av t w hax t b lwh valid data input dq0-7 (input) t whdx t d vwh ub t avax t ax av valid data input t w h dx t d vwh low address valid t ax av dq8-15 (input)
21/32 m69ar024b figure 14. write enable and ub /lb controlled, write ac waveforms 3 note: e2 = high. ai07490b t a vbl address w e 1 t avax t bhax t b lbh lb address valid t a vbl t ax av t bhax t b lbh valid data input dq0-7 (input) t b h dx t d vbh ub t avax t ax av valid data input t b h dx t d vbh low address valid t ax av dq8-15 (input)
m69ar024b 22/32 figure 15. write enable and ub /lb controlled, write ac waveforms 4 note: e2 = high. ai07489c t a vbl address w e 1 t avax t bhax t b lbh lb address valid t a vbl t ax av t bhax t b lbh dq0-7 (input) t b h dx t d vbh ub t avax t ax av t b h dx t d vbh low address valid t ax av dq8-15 (input) t b h dx t d vbh t a vbl t bhax t b lbh t a vbl t bhax t b lbh t b h dx t d vbh valid data input valid data input valid data input valid data input t b lbh2 t b lbh2
23/32 m69ar024b figure 16. chip enable controlled, read and write mode ac waveforms note: write address is valid from last falling edge of either e1 or w . ai07280c read data output address e 1 dq w t elax t eleh g t g h e l ub , lb t e ha x t ehel write address t a vel t elax (read) write data input t d veh t e h q z t e h qx t ehel t e lqv t a vel (read) read address t ehax t e ha x (read) t e h dx t e l qx t e h qx
m69ar024b 24/32 figure 17. chip enable, write enable, output enable controlled, read and write mode ac waveforms note: g can be fixed low during the write part of a read-write-read operation that is under e1 control. ai07281c read data output address e 1 dq w t elax t w lwh g t g h e l ub , lb t glqv t e ha x t ehel write address t a vel t elax (read) write data input t d vwh t e h q z t e h qx t ehel t e lqv t a vel (read) read address t w hax t e ha x (read) t w h dx t g l qx t g h qx read data output
25/32 m69ar024b figure 18. output enable and write enable controlled, read and write mode ac waveforms note: e1 can be tied low for a w and g controlled operation. when e1 is tied low, the output is exclusively controlled by g . ai07282c read data output address e1 dq w t avax t w lwh g ub , lb t glqv t ax av write address t a vwl t avax (read) write data input t d vwh t g h q z t g h qx t a vqv t ax av read address t w hax t ax av t w h dx t g l qx t ghqx read data output t g h q z low t a vgl
m69ar024b 26/32 figure 19. output enable, write enable and ub /lb controlled, read and write mode ac waveforms note: e1 can be tied low for a w and g controlled operation. when e1 is tied low, the output is exclusively controlled by g . ai07283c read data output address e1 dq w t avax t b lbh g ub , lb t b lqv t ax av write address t a vbl t avax (read) write data input t d vbh t bh q z t b h qx t a vqv t ax av read address t bhax t ax av t b h dx t bl qx t b h qx read data output t bh q z low t a vgl
27/32 m69ar024b table 9. standby mode ac characteristics note: 1. applicable also to power-up. 2. some data might be written into any address location if tehwl (min) is not satisfied. 3. the input transition time (t t ) at ac testing is 5ns as shown below. if actual t t is longer than 5ns, it may violate ac specification of some timing parameters. figure 20. power down mode ac waveforms symbol alt. parameter m69ar024b unit -70, -80 min max t clex t csp e2 low setup time for power down entry 10 ns t exch t c2lp e2 low hold time after power down entry 70 ns t ehev (1) t chh e1 high hold time following e2 high after power- down exit (sleep mode only) 300 s t chel t chh e1 high hold time following e2 high after power- down exit (not in sleep mode) 300 s t ehch t chs e1 high setup time following e2 high after power-down exit 0s t ehgl t chox e 1 high to g invalid time for standby entry 10 ns t ehwl (2) t chwx e 1 high to w invalid time for standby entry 10 ns t t (3) t t input transition time 1 25 ns ai05864b t clex e 1 power down entry e2 t exch t ch el power down mode power down exit t ehch dq high-z
m69ar024b 28/32 figure 21. power-up mode ac waveforms figure 22. standby mode entry ac waveforms, after read note: e2 = high. ai07284b e1 v cc v cc (min) 0v e2 t e h ev ai07750b t e h gl e 1 g w active (read) standby active (write) standby t e hw l
29/32 m69ar024b package mechanical figure 23. tfbga48 6x8mm - 6x8 active ball array, 0.75 mm pitch, package outline, bottom view note: drawing is not to scale. table 10. tfbga48 6x8mm - 6x8 active ball array, 0.75 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.260 0.0102 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 3.750 C C 0.1476 C C ddd 0.100 0.0039 e 8.000 7.900 8.100 0.3150 0.3110 0.3189 e1 5.250 C C 0.2067 C C e 0.750 C C 0.0295 C C fd 1.125 C C 0.0443 C C fe 1.375 C C 0.0541 C C sd 0.375 C C 0.0148 C C se 0.375 C C 0.0148 C C e1 e d1 d eb a2 a1 a bga-z26 ddd fd fe sd se e ball "a1"
m69ar024b 30/32 part numbering table 11. ordering information scheme the notation used for the device number is as shown in table 11. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest stmi- croelectronics sales office. example: m69ar024 b l 70 zb 8 t device type m69 = 1t/1c memory cell architecture mode a = asynchronous operating voltage r = 1.7 to 1.95v array organization 024 = 16 mbit (1m x16) option 1 b = 2 chip enable option 2 l = l-die speed class 70 = 70 ns 80 = 80 ns package zb = tfbga48, 6x8mm, 0.75mm pitch operative temperature 8 = C30 to 85 c shipping method t = tape & reel packing
31/32 m69ar024b revision history table 12. document revision history date version revision details 09-oct-2002 1.0 first issue 17-feb-2003 2.0 document completely revised 14-mar-2003 2.1 ac measurement load circuit revised. a19-a3 address line labelling corrected 04-apr-2003 2.2 correction to signal description in write mode section; tblqz,elqz,glqz renamed as tblqx,elqx,glqx in read mode ac characteristics; a minor label correction in a timing diagram; and value of texch(min) changed 04-jun-2003 2.3 zh (8x10mm) package removed. access time changed to 80ns, with many consequent changes to timing parameters in ac characteristics tables. ambient operating temperatures changed. some dc characteristics (and their test conditions) changed 17-jun-2003 2.4 standby current changed 25-jul-2003 2.5 power-on sequence described, and values for t ehev (min) and t chel (min) revised. 21-oct-2003 2.6 70ns and 80ns access times offered as two options
m69ar024b 32/32 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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